This invention relates to methods of forming capacitor-over-bit line memory cells.
Semiconductor processing involves a number of processing steps in which individual layers are masked and etched to form semiconductor components. Mask alignment is important as even small misalignments can cause device failure. For certain photomasking steps, proper alignment is extremely critical to achieve proper fabrication. In others, design rules are more relaxed allowing for a larger margin for alignment errors. Further, there is a goal to reduce or minimize the number of steps in a particular processing flow. Minimizing the processing steps reduces the risk of a processing error affecting the finished device.
This invention arose out of needs associated with improving the manner in which semiconductor memory arrays, and in particular capacitor-over-bit line memory arrays, are fabricated.
Methods of forming capacitor-over-bit line memory cells are described. In one embodiment, a bit line contact opening is etched through conductive bit line material. In one implementation, a bit line contact opening is etched through a previously-formed bit line. In one implementation, a bit line contact opening is etched after forming a bit line.